1. Field of the Invention
This invention relates to a phase synchronizer.
2. Discussion of Prior Art
Generally, when a signal passes through a transmission system, the signal level and phase change. If these changes are indeterminate and fluctuate in accordance with the transmission system or environment and if it is desired to obtain an output with a certain fixed phase with respect to the signal which has passed through the transmission system, a phase-locked-loop (PLL hereafter) circuit is normally used. As shown in FIG. 1, a PLL circuit typically comprises a phase comparator 1, a low-pass filter 2 and a voltage controlled oscillator 3. 4 is a signal source, 5 is a transmission system and D indicates disturbance of the transmission system.
Although a PLL circuit can readily obtain a stable output signal having a fixed phase relation with respect to and the same frequency as the input signal where the input signal is a weak signal with poor signal-to-noise (S/N), the input noise-eliminating capability of the PLL circuit is virtually determined by the capture range thereof. Consequently, when the time constant of the low-pass filter is increased and the capture range narrowed, the selectivity of the PLL circuit improves and the input noise-eliminating capability increases so that a signal with good S/N is obtained as an output even when the S/N is poor. However, in order for the PLL circuit to lock on the input signal, the capture range cannot be narrowed to an extreme--that is, a certain width is always necessary. Consequently, there is a shortcoming in that the output signal of a PLL circuit also contains a certain amount of noise as a phase component when the S/N of the input signal is poor. Also, because of the capture range of the PLL circuit, the voltage controlled oscillator must have low drift or a variable resistor for adjusting the voltage controlled oscillator is necessary.